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Miscellany

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Very first paragraph mentions v5TE instruction set architecture but there is no x-ref on Wiki. Would be nice to elaborate. --Todd 20:32, 12 July 2006 (UTC)[reply]

Was the StrongARM designed sololy by Digital, or was Acorn/ARM involved in the development process?


I was under the impression that it was designed as a joint venture.

Furthermore, I also thought that the XScale was quite a re-design, compared to the SA-1110. For example, unmodified StrongArm code runs about as fast on a 400Mhz XScale as the 206MHz SA-1110. (That's what they claim about the Sharp Zaurus SL-5500 vs 5600.) The XScale is, however, designed to be able to run at a much higher clock frequency. They have been hinting at new versions approaching 1GHz, consuming around 1W since 2000, but I haven't seen any hard evidence for this yet. - Popup 15:53, 2004 Feb 4 (UTC)

I thought it was Digitals version of Arms core modified to closely suit their process technology

Though ARM consulted on the design, the actual design work was done solely by Digital/DEC. SA-1 core was a grounds-up design within Digital, while SA-2 core is a grounds-up design within Intel. Dyl 14:24, 1 April 2006 (UTC)[reply]

Need to add details ofthe Intel IXP processors(network processors and backplane processors) which use an xscale core but also have various hardware acceleration units.Maybe seperate pages ? Some using the MSA architecture jointly developed between Intel and Analog devices. Analog use MSA in their blackfin dsp chips.

The IXP processors run at up to 1.2GHz. alxx 13:12, 20 November 2005 (UTC)[reply]

The processor list is very out of date, and somewhat misleading.

  • I have begun adding information about the other processor families, but it still neds some work. Perhaps somebody with some knowledge of these chips could add more info. Judzillah 00:06, 12 April 2006 (UTC)[reply]

Out of date? Please give more detailed info. (Mar 25/06)

I so want to see mention of the bugginess of Intel's XScale chips. Like how the PXA250 was notable for sheer bugginess, and how the PXA255 errata falsely claimed many of those bugs were fixed; and design goofage. But I suppose that doesn't belong in the body of the article. It was a real PITA in terms of getting software to work there, though. 69.226.236.175 (talk) 08:34, 26 August 2009 (UTC)[reply]

Wireless MMX

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There are some differences in the XScale MMX implementation compared to IA86 MMX worth mentioning, most notably that the destination register need not be one of the source registers, ie: 


// XScale:
mm0 = mm1 + mm2;

// IA86:
mm0 = mm1;
mm0 += mm2;

MX44 12:37, 21 July 2006 (UTC)[reply]

Sale of XScale business to Marvell

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From http://www.intel.com/pressroom/archive/releases/20060627corp.htm it looks like the "sale of XScale business to Marvell" covers only the communications and application processor business (i.e. PXA). There's no mention of the IXP business going the same way. The way this is described in the article (and in the ARM architecture article) would suggest it is.

Clarification needed. Ptoboley 12:57, 21 September 2006 (UTC)[reply]


I agree - the first paragraph states that just the PXA unit was sold, but then at the end of the article, it says the entire XScale unit was sold. I'm going to edit the end as the PXA is more accurate, and supply citation. Done, but I couldn't figure out how to get the citation to work. Please help. informedbanker 13:55, 26 September 2007 (UTC)[reply]

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